The present invention relates to integrated circuits, and more particularly, to a multiplexed flip-flop electronic device.
1. Background of the Invention
Multiplexed flip-flop devices are used in microprocessors as data path structures, for example. A multiplexed flip-flop device usually includes multiple input multiplexing means followed by a flip-flop. These two components are independent components obtained from standard component libraries. This yields a structure having a non-negligible overall surface area, relatively long signal propagation times, and high energy consumption.
2. Summary of the Invention
In view of the foregoing background, it is therefore an object of the present invention to provide a multiplexed flip-flop electronic device that includes components common to the multiplexing means and to the flip-flop, thus reducing the surface area of a corresponding integrated circuit cell.
Another object of the present invention is to use a gated clock signal to control the slave switch of the flip-flop, thus avoiding oscillation of certain nodes of the circuit, and consequently, this represents a saving in terms of energy consumption.
A further object of the present invention is to combine the means for generating the gated clock signal with the decoder logic circuit of the multiplexing means.
The invention not only economizes on overall surface area and energy consumption, but also reduces the propagation time of signals within the device, especially on the data paths and on the data input selection paths.
These and other objects, advantages and features according to the present invention are provided by a multiplexed flip-flop electronic device including multiplexing means with N inputs and one output. The multiplexing means is controlled by a decoder logic circuit, and includes the first switching stage of a flip-flop. The first switching stage is controlled by a first switching signal. The multiplexing means precedes two buffer stages which are also part of the flip-flop. Each buffer stage may be formed by two inverters connected in parallel to each other. The two buffer stages are separated by a second switching stage of the flip-flop. The second switching stage is controlled by a second switching signal.
According to one general feature of the invention, the multiplexing means include N switches that can be controlled individually, and also form the first switching stage (master switch). The decoder logic circuit delivers the first switching signal. The electronic device also includes control means receiving a clock signal, and delivers a gated clock signal forming the second switching signal.
Thus, in accordance with the invention, the first switching stage acting as the master switch of the flip-flop is also part of the multiplexing means. Furthermore, the gated clock signal that controls the second switching stage (slave switch) of the flip-flop avoids toggling of the nodes of the second switching stage. Consequently, this absence of toggling reduces energy consumption. Such toggling occurred in the prior art because the slave switch was controlled directly by the clock signal.
In one embodiment of the invention, the control means include a latch having an enable input for receiving an enable signal, a control input for receiving the inverted clock signal, and an enable output. The control means further include an AND gate having a first input connected to the enable output, a second input receiving the clock signal, and an output delivering the gated clock signal, i.e., the second switching signal.
The decoder circuit has a first control input receiving the inverted clock signal, and a second control input connected to the enable output of the latch. In other words, the first switching signal is also conditioned by the gated clock signal.
In one embodiment of the invention, the decoder circuit includes n decoder inputs, with N being equal to 2n, and N decoder AND gates. Each decoder AND gate has a first input forming the first control input, a second input forming the second control input, and n supplementary inputs connected to the n decoder inputs.